An efficient VLSI implementation of IDEA encryption algorithm using VHDL

Data security is an important issue in computer networks and cryptographic algorithms are essential parts in network security. So far, International Data Encryption Algorithm (IDEA) is very secure. In this paper, we present a VLSI implementation of the IDEA block cipher using VHDL using AMI 0.5 process technology standard cells. We have optimized the modulus multiplier and exploited the temporal parallelism available in the IDEA algorithm. In our implementation, the subkeys are generated internally once the original key is fetched. This key is retained unless a new key is used for encryption. This implementation does not employ an additional RAM to store the subkeys. Our chip contains the same eight units, and each unit can execute one round of the algorithm. Using pipelined design, eight rounds of the algorithm are executed in parallel in a chip. Our implementation operating at 10 MHz achieves a throughput of greater than 700 Mbps, which is several times higher than previous implementations.