کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
11028119 | 1666113 | 2018 | 24 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1â¯V from 1.3â¯V single supply with recovery settling time about 680â¯nsec. It can supply current from 10â¯ÂµA to 100â¯mA consuming quiescent current of 20.5â¯ÂµA and 95â¯ÂµA, respectively. It supports load capacitance from 0 to 50â¯pF with phase margin that increases from 43° at low load (10â¯ÂµA) to 74° at high load (100â¯mA) and power supply rejection ratio (PSRR) less than â20â¯dB up to 100â¯kHz. The proposed LDO is designed in 130â¯nm CMOS technology and occupies an area of 0.11â¯mm2. Post layout simulations show better performance compared with other reported techniques.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 96, November 2018, Pages 207-218
Journal: AEU - International Journal of Electronics and Communications - Volume 96, November 2018, Pages 207-218
نویسندگان
Mahmoud H. Kamel, Ahmed N. Mohieldin, El-Sayed Hasaneen, Hesham F.A. Hamed,