An area-efficient bit-serial sequential polynomial basis finite field GF(2m) multiplier

Many cryptographic and error control coding algorithms rely on finite field arithmetic. Hardware implementation of these algorithms requires an efficient realization of finite field GF(2m) arithmetic operations. Finite field multiplication is complex among the basic arithmetic operations, and it is employed in field exponentiation and inversion operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a modified interleaved modular reduction multiplication algorithm and its bit-serial sequential architecture are proposed. It is observed from the comparison of analytical results that the proposed architecture achieves the reduction in area and area-delay product compared to the existing multipliers. The proposed multiplier achieves an improvement of 39% in area and 17% in area-delay product estimations for field order of 409 when compared with the best sequential multiplier available in the literature. Application specific integrated circuit (ASIC) implementation of the proposed multiplier together with the two most comparable multipliers confirms that the proposed multiplier outperforms in terms of area and area-delay product. The proposed multiplier is suitable for implementation of security in Internet of Things (IoT) gateways and edge-devices.