Energy-efficient and security-optimized AES hardware design for ubiquitous computing*

Ubiquitous computing must incorporate a certain level of security. For the severely resource con-strained applications, the energy-efficient and small size cryptography algorithm implementation is a critical prob-lem. Hardware implementations of the advanced encryption standard (AES) for authentication and encryption arepresented. An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices. It proves that compact AES architectures fail to optimize the AES hardware energy, whereas reducinginvalid switching activities and implementing power-optimized sub-modules are the reasonable methods. Implemen-tations of different substitution box (S-Boxes) structures are presented with 0.25 μm 1.8 V CMOS (complementarymetal oxide semiconductor) standard cell library. The comparisons and trade-offs among area, security, and powerare explored. The experimental results show that Galois field composite S-Boxes have smaller size and highestsecurity but consume considerably more power, whereas decoder-switch-encoder S-Boxes have the best power char-acteristics with disadvantages in terms of size and security. The combination of these two type S-Boxes instead ofhomogeneous S-Boxes in AES circuit will lead to optimal schemes. The technique of latch-dividing data path isanalyzed, and the quantitative simulation results demonstrate that this approach diminishes the glitches effectivelyat a very low hardware cost.