کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
1713217 1519809 2006 5 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Design and implementation of a high-speed reconfigurable cipher chip
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه سایر رشته های مهندسی کنترل و سیستم های مهندسی
پیش نمایش صفحه اول مقاله
Design and implementation of a high-speed reconfigurable cipher chip
چکیده انگلیسی
A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfiguration analysis of algorithms, the design of reconfigurable processing units and a new reconfigurable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the operating frequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Systems Engineering and Electronics - Volume 17, Issue 4, December 2006, Pages 712-716
نویسندگان
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