A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantization noise

• A new digital pixel design for IR detector arrays have been proposed.
• Pixel design is based on PFM and extended integration.
• 2.33 Ge− charge handling capacity and quantization noise of 161 e− have been measured.
• Very low figure of merit for power effectiveness 465 fJ/LSB reported.
• Fast frame rates up to 400 Hz can be achieved using the proposed digital pixel.

This paper represents a novel digital readout for infrared focal plane arrays with 2.33 Ge− charge handling capacity while achieving quantization noise of 161 e−. Pixel level A/D conversion has been realized by pulse frequency modulation (PFM) technique supported with a novel method utilizing extended integration that eliminates the requirement for an additional column ADC. Digital pixel operates with two phases; the first phase is as ordinary PFM in charge domain and the second phase is in time domain, allowing the fine quantization and low quantization noise. A 32 × 32 prototype has been manufactured and tested. Measured peak SNR at half well fill is 71 dB with significant SNR improvement for low illuminated pixels due to extremely low quantization noise. 32 × 32 ROIC dissipates only 1.1 mW and the figure of merit for power dissipation is measured to be 465 fJ/LSB, compared to 930 fJ/LSB and 1470 fJ/LSB of the state of the art.