A low power cryogenic 512 × 512-pixel infrared readout integrated circuit with modified MOS device model

• A MOS device model for circuit simulation at cryogenic temperatures is designed.
• A CTIA with inherent CDS is used to realize a high performance interfacing circuit.
• Optimized readout timing and structure are applied to reduce the power consumption.
• The readout integrated circuit can satisfy large array system requirement.

A low power cryogenic readout integrated circuit (ROIC) for 512 × 512-pixel infrared focal plane array (IRFPA) image system, is presented. In order to improve the precision of the circuit simulation at cryogenic temperatures, a modified MOS device model is proposed. The model is based on BSIM3 model, and uses correction parameters to describe carrier freeze-out effect at low temperatures to improve the fitting accuracy for low temperature MOS device simulation. A capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CDS) configuration is employed to realize a high performance readout interfacing circuit in a pixel area of 30 × 30 μm2. Optimized column readout timing and structure are applied to reduce the power consumption. The experimental chip fabricated by a standard 0.35 μm 2P4M CMOS process shows more than 10 MHz readout rate with less than 70 mW power consumption under 3.3 V supply voltage at 77–150 K operated temperatures. And it occupies an area of 18 × 17 mm2.