Optimization of SFQ Logic Gate Considering Dependence of its Signal Propagation Delay on the Bias Voltage

Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. The operating margin of an SFQ logic circuit generally decreases with an increase in the operating frequency because of the timing error in the low-bias region caused by the difference in bias dependence of the signal-propagation delay between the data and clock lines. We proposed an improvement in the operating margin by controlling the dependence of the signal-propagation time on the bias voltage. In the present study, we investigated a new optimization method for an SFQ logic gate. We developed a new circuit parameter optimizer, which takes into account not only the bias margin but also the dependence of the signal-propagation delay on the bias voltage. We defined an appropriate evaluation function for the optimization. From the result of the optimization using the defined evaluation function, we designed and demonstrated an SFQ AND gate optimized using the new optimizer.