From Error to Error: Logic Debugging in the Many-Core Era

Design and manufacturing of present day Multi-Core microprocessors has to overcome major technology obstacles, particularly in the areas of Power and Validation. More specifically, the state of the Art in the area of validation is such that upwards of 30% of the human resources in a modern microprocessor Design Team are dedicated to it. The term Validation Productivity Gap has been introduced to describe exactly these ever increasing resource requirements. Formal Verification techniques offer one of the technological approaches for addressing many aspects of this validation gap. Therefore it is of paramount importance to develop technologies and methodologies for reducing the time it takes to debug and rectify Logic Errors that are detected by Formal Verification Techniques. Such developments would offer a much needed productivity improvement both in pre- and post-Silicon validation activities.