High-performance forward error correction: Enabling multi-gigabit flows and beyond on commodity GPU and CPU hardware in presence of packet loss

• We propose parallel design of FEC coding applicable to both CPU and GPU architectures.
• Our scheme can manage multi-gigabit flows.
• We deploy our scheme in low-latency real-time multimedia transmissions over IP networks.
• We provide extensive evaluation in realistic scenarios.

In demanding real-time multimedia transmissions, even a small packet loss might significantly degrade the visual quality. As retransmission is not an option in real-time transfers especially when transmitting the data over long distances, it is necessary to employ mechanisms of Forward Error Correction (FEC). Low-Density Generator Matrix (LDGM) codes are known to be suitable for coding on large block sizes, however, high bitrates of currently used video formats (FullHD, 4K) also require high throughput of FEC coding and decoding. We propose a parallel design of LDGM encoding and decoding algorithms suitable for off-the-shelf, (massively) parallel platforms, such CPUs with vector units or GPUs, and evaluate our approach in real-world scenarios of high-definition and 4K video transmissions. Our results show that offloading FEC computation to such platform is beneficial for low-latency, high-quality multimedia transmissions and may even enable transmissions beyond 10Gbps once the commodity network interfaces reach this speed.