An algorithm for fast multiplication of sedenions

In this work a rationalized algorithm for calculating the product of sedenions is presented which reduces the number of underlying multiplications. Therefore, reducing the number of multiplications in VLSI processor design is usually a desirable task. The computation of a sedenion product using the naive method takes 256 multiplications and 240 additions, while the proposed algorithm can compute the same result in only 122 multiplications (or multipliers – in hardware implementation case) and 298 additions.

► We propose fast algorithms for two sedenions multiplication.
► We interpret the multiplication of sedenions as vector–matrix product.
► The matrix participating in the matrix–vector multiplication can be decomposed, which leads to an efficient algorithm.
► As a result the number of multiplications is reduced by half.