CMOS design of a low power and high precision four-quadrant analog multiplier

In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2 V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35 μm standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1 MHz, a −3 dB bandwidth of 485 MHz and a maximum power consumption of 0.232 mW while the static power consumption is 0.111 mW.