Efficient implementation of a frame aggregation unit for optical frame-based switching

Aggregating Ethernet frame or IP packet in large fixed-size frames allows for building scalable core network architectures. Classifying the arriving traffic based on destination core node information and quality of service parameters alleviates the need of performing table look-ups on packet basis. These advantages come at the cost of extra logic at the network egress, as regards implementation, and additional jitter due to the frame assembly process. This paper describes the efficient implementation of a frame aggregation unit that gathers Ethernet packets in G.709 containers, handles 10 Gb/s links, performs classification based on 24-byte headers, and includes a highly pipelined Queue Manager to cope with the considered rates while a specific scheduler controls the quality of service per core network flow. Based on the developed demonstrator, we provide results both as regards area and performance for an FPGA (field programmable gate array) Virtex-4 implementation as well as regarding the introduced jitter.