کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
446579 1443166 2013 12 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A methodology for implementing decimator FIR filters on FPGA
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
A methodology for implementing decimator FIR filters on FPGA
چکیده انگلیسی

This paper presents a methodology which can be used to implement any decimator symmetric/antisymmetric (S/A) finite impulse response (FIR) filter. Two varieties are developed: a classic distributed arithmetic (CDA) based and a modified distributed arithmetic (MDA) based one. Both exploit the polyphase structure and the symmetry/antisymmetry of the filter and are evaluated in terms of area efficiency, speed and power consumption. The choice of the algorithm depends on the performance metrics targeted. The methodology has been applied to implement the filter bank CDF9/7 which constitutes a one dimensional (1D) and one level discrete wavelet transform (DWT). The filter bank also known as the bior4.4 biorthogonal wavelets is recommended by the JPEG2000 standard for lossy compression of images and video. The architecture has been implemented on an Altera field programmable gate array (FPGA) and the simulations run in Matlab, Modelsim and Altera Quartus II. The results prove the efficiency of the algorithms and show the tradeoff between the area occupied, the throughput and the power consumption.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 67, Issue 12, December 2013, Pages 993–1004
نویسندگان
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