A dual-rate burst-mode bit synchronization and data recovery circuit with fast optimum decision phase calculation

A novel burst-mode bit synchronization and data recovery circuit for use in passive optical networks are presented that can operate at either 1.25 Gb/s or 622 Mb/s. The circuit principle is based upon shifting the incoming burst such that its maximum eye opening is phase aligned with the rising edges of an external, fixed reference clock. This is accomplished by oversampling the incoming data signal by a factor 10. During the preamble of each burst, the correct phase shift is calculated from these samples using a fast, digital algorithm, which determines the correct phase shift using 20 bits from the preamble of each burst. The digital algorithm combines centre phase picking with majority voting to increase robustness against noise. Once the fast determination of the required phase shift is finished, the circuit switches to a tracking mode, and tracks the optimum phase shift alongside the entire burst length. At least 72 consecutive identical digits can be tolerated. The circuit was implemented in a 0.13-μm0.13-μm CMOS technology. Measurement results are reported, which confirm the operation of the presented circuit.