کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
447040 1443204 2010 5 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Linearization technique using bipolar transistor at 5 GHz low noise amplifier
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
Linearization technique using bipolar transistor at 5 GHz low noise amplifier
چکیده انگلیسی

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 64, Issue 10, October 2010, Pages 978–982
نویسندگان
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