High speed switched-current memory cell with very low offset and charge injection errors

In this paper a high speed class AB switched-current memory cell is presented. Memory transistors have been designed in triode region in order to reduce the threshold voltage mismatch and clock feed-through errors. Also a modified Flipped Voltage Follower (FVF) circuit is used to cancel charge injection error. Besides, this cell consists of a new common-mode feedforward (CMFF) circuit which attenuates the common mode components and improves offset error at output. Furthermore, a coupled differential (CDR) memory cell (MC) is used to eliminate the clock feedthrough (CFT) error considerably. All of the presented circuits have been designed by using TSMC 0.18 μm process parameters and simulated in HSPICE. Simulation results show that maximums of THD, SNR and SFDR at clock frequency of 100 MHz and 1 MHz as input frequency are –71 dB, 71.2 dB and 68 dB respectively. Obtained results demonstrated considerable improvement in the circuit performance which confirm the excellence of proposed memory cell in comparisons to previous cells.