کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
447521 1443145 2015 10 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Fast physical design of CMOS ROs for optimal performance using constrained NSGA-II
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
Fast physical design of CMOS ROs for optimal performance using constrained NSGA-II
چکیده انگلیسی

The performance of nanoscale radio frequency integrated circuits (RFIC) is influenced by the circuit parasitics and device dimensions. The present work predicts the design parameters of CMOS ring oscillator (CMOS RO) for its optimal performance and designs the CMOS RO using these parameters in Cadence Virtuoso Analog Design Environment with GPDK 90 nm process. An efficient optimization technique, non-dominated sorting based genetic algorithm (NSGA-II) is used to minimize the power consumption and phase noise of the circuit at its schematic and physical levels. This optimization is also carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and by considering the variations in the process parameters. The optimization algorithm, effectively converts several time consuming design iterations to a single step design, ensuring the near best performance of the CMOS RO with all possible real time constraints. In this proposed design methodology the optimization objectives such as frequency, power and phase noise are formulated in such a manner that those are implicitly parasitic aware. The design of CMOS RO with different number of stages is verified by performing simulations for transient and noise analysis using Cadence tools.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: AEU - International Journal of Electronics and Communications - Volume 69, Issue 9, September 2015, Pages 1233–1242
نویسندگان
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