Design of a mixed-signal digital CMOS fuzzy logic controller (FLC) chip using new current mode circuits

Presented in this paper is design of a new FLC chip with mixed-signal (analog and digital) inputs and digital outputs. This work is based on a new strategy in which analog advantages such as low die area, high speed and simplicity are added to the system advantages, whose output is digital considering unchanged digital system properties. For implementing this idea, a new programmable Fuzzifier circuit based on mixed-signal input and generation of three different current membership functions including Gaussian, Trapezoidal and Triangular shapes are proposed. To contribute antecedents in inference block, three new integrated circuits for implementing Min–Max operators are proposed. We improved and designed a Multiplier/Divider circuit and a current mode Analog to Digital (A/D) converter with 7bit resolution to complete and implement Defuzzifier block. The proposed controller circuit which consists of two inputs, four membership functions for each one, sixteen rules and one output designed less than 0.1 mm2 area in 0.35 μm CMOS standard technology. The systematical simulation results of MATLAB software was compared to the HSPICE simulation results using extracted circuit layout. The inference speed of the controller is about 16.6 MFLIPS.