Topology selection for high-precision Vernier digital-to-time converters in standard CMOS

This paper presents two architectures that apply the Vernier delay line principle to the field of digital-to-time conversion. Both architectures are compared in terms of variability, power consumption, and area. The results show that the optimal architecture depends on the required delay resolution, on technology parameters, and on the relative importance given to power and area. If the required resolution is much smaller than the unit delay and single-shot precision is important, a topology using a matrix of delay elements provides a better power-mismatch tradeoff. If the required resolution is modest, if there is a stringent area spec, or if the focus is on linearity rather than single-shot precision, a dual delay line topology is to be preferred. The paper also derives a Pelgrom-like mismatch law for propagation delay, which can be used in the design of different types of circuits and will become more valid in future CMOS generations.