A model for communicating long synapses with guaranteed latencies on large neural networks

This paper introduces a new approach for the implementation of randomly interconnected neural networks on hardware taking into account the length of the synapses. We divide the synapses into Long and Short according to the distance between the source and target neurons in a 2D mesh, and we demonstrate that it is possible to guarantee the latency of the Long synapses when they are routed through an additional layer which is based on hierarchical structures of Networks on Chip (NoC). The connection scheme consists in grouping neurons into four regions and communicating their sets of synapses between a pair of them, using circuit switching. In order to validate the interconnection scheme, we simulated the operation of this additional layer for two regions in a neuronal network with grid structure arrangement comprising 1.03 × 106 neurons, with a firing rate of 100 Hz and an average of 104 synapses per neuron. This pair of regions can support an average of 562 Long synapses per neuron, which is equivalent to managing 5% of the traffic generated by the grouped neurons, with the advantage of having the latency of the synapses guaranteed. A node of the one region has 30,528 neurons and operates with a throughput of 2.95 Millions of spikes per second (Mspk/s) approximately. In a complete operation, the additional layer has four regions and it would support 58 Mspk/s and 520,672 neurons of the network.