Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

• A high-throughput low-latency network for snoop-based cache coherence protocol is proposed.
• Execution time and power consumption are reduced meanwhile area over-head is kept low.
• Benefits rely on the synergy between the snoop protocol and the high-throughput network.

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-on-chip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol – and hence its resources – and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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