A novel clock generation algorithm for system-on-chip based on least common multiple

• An algorithm to generate the clocks for the different cores in a System-on-Chip (SoC) is proposed.
• The algorithm minimizes the number of Phase Locked Loops (PLLs) required in a SoC.
• As a result, the power consumed by the clock generator circuit of a SoC can be reduced.
• Design cost and area of a SoC can also be minimized.

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.

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