Implementation of Digital Electronic Arithmetics and its application in image processing

In this paper we introduce new algorithm implementations of a new parametric image processing framework that will accurately process images and speed up computation for addition, subtraction, and multiplication. Its potential applications include computer graphics, digital signal processing and other multimedia applications. This Parameterized Digital Electronic Arithmetic (PDEA) model replaces linear operations with non-linear ones. The implementation of a parameterized model is presented. We also present the design of arithmetic circuits including parallel counters, adders and multipliers based in two high performance threshold logic gate implementations that we have developed. We will also explore new microprocessor architectures to take advantage of arithmetic. The experiments executed have shown that the algorithm provides faster and better enhancements from those described in the literature. The FPGA chips used is Spartan 3E from Xilinix. The critical length in the circuit implemented on the FPGA had the minimum period for the proposed subsystem is 10.209 ns (maximum frequency 97.957 MHz). Maximum power consumed is 2.4 mW using 32 nm process and we used parallelism and reuse of the Hardware components to accomplish and speed up the process.