An EDA tool for implementation of low power and secure crypto-chips

Regarding the significant mathematical immunity of recent cryptographic algorithms, attacks considering the physical aspects of these algorithms, known as side channel attacks, have received much of interest. Today, it is quite clear that asynchronous circuits possess considerable inherent countermeasure capabilities against side channel attacks, and therefore they are more immune for cryptographic systems compared to synchronous design. However, due to lack of automatic synthesis and optimization tools for these circuits, implementation of secure asynchronous circuits encounters many difficulties. In this paper, a fully automated secure design flow and a set of secure library cells resistant to power analysis and fault injection attacks are introduced for quasi delay insensitive asynchronous circuits. In the proposed flow, a high-level description of the system is received in Verilog format powered by some special macros, and then the corresponding specification will be decomposed into smaller circuits directly mappable to predefined circuit templates. With the use of a special standard-cell library, the final circuit is resistive to differential power analysis on faulty hardware attack. We suggest a restructuring on the conditional statements in the high-level description of the circuit which leads to a considerable optimization in power consumption after the decomposition of the system. To verify the efficiency of our presented design flow, we implemented data encryption standard (DES) and advanced encryption standard (AES) algorithms, and we showed 23% less power consumption compared to the existing data driven decomposition asynchronous synthesis method. Also, these implementations are three times faster than the synchronous implementations on average, in TSMC 0.18 μm technology.