A NAND flash management algorithm with limited on-chip buffer resource

Wear-leveling algorithm is one of the key technologies in optimizing the endurance as well as the performance for a NAND flash memory-based system. An efficient wear-leveling algorithm, based on the combination method of the block-mapping table and page-mapping table with only very limited on-chip buffer resource, is proposed in this paper. This algorithm has excellent power-cycle reliability, and is flexible for those embedded digital storage applications in which the on-chip buffer resource for mapping table and data buffer is limited. For those applications, any additional memory chip applied as large mapping table or payload data buffer space is not accepted, considering the form-factor size or material cost. A real silicon chip, as a NAND flash controller without auxiliary buffer, was realized to apply this algorithm. Its efficiency and performance have been silicon-proven.