A systematic approach to configurable functional verification of HW IP blocks at transaction level

With demand growing by the day, the complexity of electronic devices is constantly increasing. Since simulation is still the most used approach, functional verification has become one of the major bottlenecks in the design and verification flow.In this paper we propose a systematic approach to configurable functional verification of electronic devices. Based on a black box approach, it can be applied to any design where behavior can be expressed by a set of functions. It combines simulation- and assertion-based verification into a hybrid verification. The proposed specification-based coverage metric can be configured ranging from a very rapid to an exhaustive verification. The approach uses Transaction Level (TL) modeling to raise the abstraction level, providing faster verification. The results of the proposed design and verification flow, Intellectual Property (IP) and Test Bench (TB) are reusable.The approach is demonstrated on two case-studies; a video-processing IP block and universal serial bus host controller. The results consider both simulation times and TB generation times.

.Figure optionsDownload as PowerPoint slideHighlights
► Proposal of a systematic approach to configurable functional verification of electronic devices.
► The approach can be applied on any design where behavior can be expressed by a set of functions.
► It combines a simulation- and assertion-based verification into a hybrid verification.
► We demonstrate it on two case-studies: a video-processing IP block and universal serial bus host controller.