Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors

Process variations in advanced nodes introduce significant core-to-core performance differences in multi-core architectures. These intra-die variations have a strong spatial correlation, leading to potential large variations among clusters of cores. Isolating each core with its own frequency and voltage island improves the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-core communication suffers from additional cross-clock-domain latencies that can offset the performance benefits. This work proposes the concept of the configurable, variable-size frequency and voltage domain, and it is described in the context of a tile-based multi-core architecture. The number of domains is determined on a chip-by-chip basis based on process variation. We observe that the optimal size of the frequency and voltage domain can range from full die to single core depending on the workload characteristics and the degree of process variation.

► Intra-die process variations lead to potentially large performance variations among clusters of cores in single-chip multi-core architectures.
► Operating each core at the highest possible frequency in its own clock domain requires a cross clock-domain latency overhead for inter-core communications.
► A variable-size frequency and voltage domain that can be configured on a chip-by-chip basis is proposed.
► The optimal size of each domain depends on the process variation and the inter-core workload communication characteristics.