Dynamic partial reconfigurable Viterbi decoder for wireless standards

In this paper, a high speed and low power runtime dynamically reconfigurable Viterbi decoder architecture with constraint lengths 3–7 with different code rates is proposed for different wireless standards. The proposed architecture uses an improved modular implementation of Add Compare Select (ACS) and Trace back units to obtain high speed. With a throughput of 81 Mbps, the architecture is suitable for use in receivers of 802.11a wireless local area network, 3G cellular code division multiple access environments, UMTS and EDGE. The proposed architecture gives high performance without any pipelining or parallelism in ACS and shows at least 13% throughput and 5× power improvement over the reported architectures. To verify the efficacy of this dynamic partial reconfigurable (DPR) Viterbi decoder method, a conventional multiplexer based reconfigurable architecture was designed and tested. DPR based technique shows 27% of resource saving and the reconfiguration time is reduced about 1/9 compared to the static reconfiguration.

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► A high speed, low power dynamically reconfigurable Viterbi decoder is proposed.
► An improved modular design of Add Compare Select (ACS) and Trace back units reduces critical path delay.
► With a throughput of 81 Mbps, the proposed architecture is suitable for 802.11a, CDMA, UMTS and EDGE.
► An application of dynamic partial reconfiguration reduces area and configuration time.