Design of priority-based active queue management for a high-performance IP switch

Multimedia services such as IPTV and video conferencing constitute a substantial portion of the traffic sources in new communication systems requiring high-speed IP switching. This paper presents a scalable architecture for a high-performance IP switch based on Priority Active Queue Management (PAQM), which provides multimedia services with improved quality of service (QoS) in the communication system. Better QoS, in terms of delay, throughput, and loss rate, can be provided by a packet scheduling technique and a buffer management architecture for packet switching networks. The proposed architecture consists of a PAQM with a dedicated memory management data structure based on circular linked lists. The linked lists include different priority levels in a pipelined organization for the management of active queues. The architecture also scales dynamically to support a large number of priority levels and a large queue size. A performance analysis of an optimized PAQM algorithm is presented using an NS-2 network simulator to evaluate the capacity of the IP switch to support QoS. The results show that this system can achieve the maximum throughput with low levels of delay. To achieve high performance, we have implemented the proposed algorithm using 0.35-μm CMOS technology, the performance of which is subsequently analyzed.

Figure optionsDownload as PowerPoint slideHighlights
► We propose a novel high performance IP switch architecture with Quality of service requirements.
► We examine simulation results using NS-2 network simulator before designing the architecture.
► A multi-level priority active queue management conceptual framework is used to implement QoS for different data flow.
► Hardware design and validation of the IP switch is done at different abstraction levels.
► The complexity of the circuit remains reasonable and the circuit is being able to operate at 250 MHz.