HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture

As the integration of transistors on today’s embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the salient problem, since regarding to the inaccessible failures of on-chip elements, there must be some levels of embedded fault tolerance techniques. In this paper, an innovated technique is revealed providing fault tolerance in the on-chip networks over single and multiple permanent switch failures. The experimental results achieved by the system simulation in SystemC TLM environment are validated with the mathematical analysis modeled for system reliability that we extend in this paper, which demonstrate the extensive reliability enhancement of this paradigm. Along with the system improvement, silicon area overhead is calculated utilizing VHDL low level simulation and Orion synthesis.

Figure optionsDownload as PowerPoint slideHighlights
► A fault-tolerant architecture for NoC using hot and cold spare switches for cores.
► Tackling with single and double switch failures in mesh topology by HACS architecture.
► Validation of SystemC network simulation with analytical model of system reliability.
► HACS achieves up to 95% reliability improvement with 29.33% area overhead in 4 × 4 mesh.
► HACS architecture degrades communication cost by 23.6% due to data flow minimization.