A novel two-fold state skip logic Built-In Self-Test scheme for digital circuits

• Two fold state skip logic determines the next consecutive useful states.
• Minimizes the test sequence length, which, in turn, helps to reduce the memory size.
• Usage of a reduced test sequence minimizes power dissipation during testing period.
• Achieved low scan power by skipping long scan switching activities.

Recent developments in the field of very-large-scale integration (VLSI) testing have led to a demand for fault diagnosis in very-large-scale integration circuits. However, the problem of test pattern generation becomes very difficult as the size of circuits increases. Proficient techniques for test pattern generation are necessary to reduce the test sequence length and testing time. In conventional methods, Automatic Test Pattern Generation (ATPG) and Design for Test (DFT) are used for test pattern generation and fault insertion in netlist files. The complexity faced in Automatic Test Pattern Generation exponentially increases with respect to the circuit size. In circuits with a large number of stuck-at-fault errors, the conventional verification sequence fails to provide acceptable fault coverage and low power consumption. A twofold state skip (TFSS) logic is developed to achieve a low scan power by skipping long scan chains to reduce switching activities. This work addresses the above-mentioned issues faced in Automatic Test Pattern Generation in VLSI circuits and examines all detectable faults using a twofold state skip logic. The proposed approach is efficient and verified on ISCAS 89 & 85 benchmark circuits; the results indicate a considerable reduction in the test data volume and thus a significant reduction in power consumption.

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