Fault diagnosis in reversible circuits under missing-gate fault model

This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an (n × n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate, yields an easily testable design, which admits a universal test set (UTS) of size (n + 1) that detects all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) in the circuit. Furthermore, storage of only one vector (seed) of the UTS is required; the rest can be generated by n successive cyclic bit-shifts from the seed. For fault location under the SMGF model, a technique for identifying the faulty gate is also presented that needs application of a single test vector, provided the circuit is augmented with some additional observable outputs.

A reversible circuit of size 3 with depth 5. Design-for-testability (DFT) of the above circuit. Universal test set of the modified circuit.Figure optionsDownload as PowerPoint slide