A survey on energy-efficient methodologies and architectures of network-on-chip

• We present an overview of the research conducted on Network-on-Chip (NoC).
• We emphasize on the energy efficiency of the NoC architectures and methodologies.
• We present taxonomies of buffered, bufferless, and energy efficient routing schemes.
• Strengths and weaknesses of the discussed techniques are highlighted.
• The survey also highlights possible directions for future research.

Integration of large number of electronic components on a single chip has resulted in complete and complex systems on a single chip. The energy efficiency in the System-on-Chip (SoC) and its communication subset, the Network-on-Chip (NoC), is a key challenge, due to the fact that these systems are typically battery-powered. We present a survey that provides a broad picture of the state-of-the-art energy-efficient NoC architectures and techniques, such as the routing algorithms, buffered and bufferless router architectures, fault tolerance, switching techniques, voltage islands, and voltage-frequency scaling. The objective of the survey is to educate the readers with the latest design-improvements that are carried out in reducing the power consumption in the NoCs.