A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.

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► The horizontal plane network of 3D NoC adopts De Bruijn graph as topology.
► Enhanced pillars are used for vertical connections.
► The General Shifting based Routing Algorithm ensures the simplest logic area for 3D NoC.
► The shortest shifting based routing algorithm provides the shortest routing path for 3D NoC.
► Fault tolerant routing is used to guarantee reliable data transmission.