Decimal Goldschmidt: A hardware algorithm for radix-10 division

A decimal Goldschmidt (DG) division architecture is presented, where the underlying algorithm is described by an optimized RTL (Register Transfer Language) code that allows pipeline realization of the two independent multiplications within DG iterations. An especial redundant digit rectangular multiplier is designed, as the main DG component, with reduced operand width based on a particular error analysis scheme. Pre-scaling the divisor via preloaded look-up tables helps in reducing the number of DG iterations, where at most four (out of sixteen) decimal digits of the divisor are stored based on a particular precision analysis. Synthesized based evaluation of the proposed designs is reported.