Design and verification of an efficient WISHBONE-based network interface for network on chip

• Deals with asynchronous FIFO based WISHBONE compatible high speed NI for NoC.
• Acts as dual purpose NI to interface synchronous as well as asynchronous IPs with routers.
• Different encoded FIFOs (binary, Gray, Johnson, and one-hot) are designed and analyzed.
• NI offers less latency due to low latency packing and unpacking, asynchronous FIFOs units.
• NI is verified using coverage driven constraint random based verification environment.

In this paper, a generic asynchronous First In First Out (FIFO) based WISHBONE compatible plug and play Network Interface (NI) for Network on Chip (NoC) is designed and verified. Four different types of encoded asynchronous FIFOs namely binary, Gray, one-hot and Johnson are designed and analyzed. It is found that Gray-code asynchronous FIFO is the best to handle the asynchronous clock domain issues in NI. The control signals of the WISHBONE bus wrappers from/to asynchronous FIFOs and packing/unpacking modules are asserted concurrently at the same rising edge of the respective router and IP clocks to reduce the latency. The same NI has been utilized for transferring data between synchronous as well as asynchronous clock domains irrespective of clock frequency and phase differences. The proposed NI ensures the seamless high data throughput between the routers and IP cores with minimal latency, higher throughput, higher speed and utilized lesser area compared to the existing design.