A novel folded-torus based network architecture for power-aware multicore systems

• A folded-torus based reduced-switch power-aware multicore system is proposed.
• In this proposal, nodes are separated between network switches and computing cores.
• Using folded-torus concept, a scheme to connect the switches and cores is developed.
• Experimental results show that the proposed system outperforms RAW, TriBA, and LBDR.
• Total power consumption and average delay are reduced by 71% and 58%, respectively.

Multicore computers are expected to be used to process a higher volume of data in the future. Current mesh-like multicore architecture is inadequate to increase memory-level-parallelism because of its poor core-to-core interconnection topology. In some architecture, each node has communication and computation components – switching component of such a node consumes power while the node is only computing and vice versa. In this paper, we propose a folded-torus based topology to improve performance and energy saving. In this architecture, nodes are separated between network switches and computing cores. Using folded-torus concept, we develop a scheme to connect the components (switches and cores) of a multicore architecture. Experimental results show that the proposed architecture outperforms Raw Architecture Workstation (RAW), Triplet Based Architecture (TriBA), and Logic-Based Distributed Routing (LBDR) architecture by reducing the switches more than 53%, the power consumption by up to 71%, and the average delay by up to 58%.

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