A real-time embedded architecture for SIFT

SIFT has shown a great success in various computer vision applications. However, its large computational complexity has been a challenge to most embedded implementations. This paper presents a low-cost embedded system based on a new architecture that successfully integrates FPGA and DSP. It optimizes the FPGA architecture for the feature detection step of SIFT to reduce the resource utilization, and optimizes the implementation of the feature description step using a high-performance DSP. Due to this novel design, this system can detect SIFT feature and extract SIFT descriptor for detected features in real-time. Extensive experiments demonstrate its effectiveness and efficiency.

► A FPGA + DSP architecture is proposed to implement SIFT algorithm in real-time.
► The proposed design integrates the parallelism of FPGA and the flexibility of DSP.
► We explore the parallelism of SIFT algorithm to improve the processing speed.
► The processing speed of this design is 150 times faster than the previous design.