Saving register-file static power by monitoring instruction sequence in ROB

Modern information technology (IT) applications make microprocessors require not only high performance, but also low power-consumption. To enhance computational performance, many instruction level parallelism techniques have been implemented in current microprocessors, e.g., data forwarding, out-of-order execution, register renaming etc. The reorder buffer (ROB) and the register file are the two most critical components to implement these features. The cooperation of them, however, causes serious static-power consumption on a physical register file which stores a large amount of speculative and committed temporary values. In this paper, we use the Pentium 4-like processor as the baseline architecture and propose a runtime approach to save the physical register file’s static power. In this approach, a monitoring mechanism is built in the ROB and the register file to identify the timing of usage for each register. This mechanism can be integrated with a DVS approach on the datapath to power down (or up) the supply voltages to a register when it is idle (or active). Simulation results show that by this monitoring mechanism and a low-cost DVS design, a 128-entry register file can save at least 50% register file power consumption.