An ASIC implementation of a low power robust invisible watermarking processor

Digital watermarking is the process of embedding data called watermark into a multimedia object so that it can be detected or extracted later to make an assertion about the object. Several software implementations of watermarking algorithms are available, but very few attempts have been made for hardware implementation. The objective of this research paper is to implement “low power robust invisible binary image watermarking processor” in an Application Specific Integrated Circuit (ASIC) using Hardware Description Language (HDL). An 8-bit processor has been used since it consumes less power than other higher order bit (16-bit, 32-bit, etc.) processors. The proposed invisible watermarking algorithm is implemented in spatial domain. The proposed algorithm is prototyped (i) using XILINX FPGA (ii) using ASIC. To the best of our knowledge this is the first low power binary image watermarking processor implemented in ASIC which uses 8-bit processor with no limitation on input size. The algorithm is tested in Virtex E (xcv50e-8-cs144) Field Programmable Gate Arrays (FPGA) and implemented in an ASIC.