Towards real time implementation of reconstructive signal processing algorithms using systolic arrays coprocessors

Reconstructive signal processing algorithms encompass a broad spectrum of computational methods. Fortunately, most of the methods fall into the classes of the matrix algebraic calculations, convolution, or transform type algorithms. These algorithms possess common properties such as regularity, locality and recursiveness. Considering such general class of reconstructive signal processing (SP) techniques, in this paper we propose a new Hardware/Software (HW/SW) co-design paradigm for the implementation of reconstructive SP algorithms via efficient systolic arrays integrated as digital SP coprocessors units. In particular, the selected matrix–matrix and matrix–vector multiplication algorithms are implemented in a systolic computing fashion that meets the real time SP system requirements when employing the developed Hardware/Software Co-Design method oriented at the use of a Xilinx Field Programmable Gate Array (FPGA) XC4VSX35-10ff668.