A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs

The derivation of efficient, custom architectures for implementing algorithms on Field Programmable Gate Array platforms presents several research challenges. We focus on the derivation of efficient streaming architectures from dataflow graphs, targeting multi-cycle, fully pipelined functional units. In this paper, we present a Force-Directed Scheduling based algorithm for deriving area-efficient architectures from dataflow graphs based on replication and critical path relaxation. We have implemented this algorithm in a design tool called CHARGER, which integrates schedule generation with post-schedule communications infrastructure generation and Hardware Description Language generation. We compare the performance of our algorithm against that of a traditional Force-Directed Scheduling approach by generating architectures from algorithms selected from embedded computing and scientific computing.