High-level design space exploration for adaptive applications on multiprocessor systems-on-chip

This paper presents an abstract design and analysis framework for applications on multiprocessor systems-on-chip (MPSoCs). The aim is to allow for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support to deal with important design decisions in the early design stage. Our framework enables design space exploration in order to identify adequate parallelism levels for hardware/software mappings in presence of adaptive system behaviors. For this purpose, we use an activation clock-based encoding in which an application is represented according to its event occurrences with their precedence relations. Then, different mapping and scheduling scenarios of applications on MPSoC are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. A number of experiments are performed to compare with state-of-the-art techniques based on synchronous dataflow graphs. Experimental results show that our framework provides a similar level of precision and efficiency. In addition, our framework is more flexible to deal with both application and platform adaptive behaviors, while allowing customized communication and computation behavior simulations.