کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
460654 696410 2012 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
چکیده انگلیسی

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the FPGA-based implementation of 2-D convolution with medium–large kernels. It is a multiplierless solution based on Distributed Arithmetic implemented using general purpose resources in FPGAs. Our proposal is modular and coefficient independent, so it remains fully flexible and customizable for any application. The architecture design includes a control unit to manage efficiently the operations at the borders of the input array. Results in terms of occupied resources and timing are reported for different configurations. We compare these results with other approaches in the state of the art to validate our approach.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Systems Architecture - Volume 58, Issue 8, September 2012, Pages 277–285
نویسندگان
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