Reconfigurable Networks on Chip: DRNoC architecture

To cover the complexity of future systems, where thousands and hundreds of heterogeneous cores have to be interconnected, new on-chip communication solutions are being searched. In this context, Networks on Chip (NoCs) have been studied as bus alternative. However, the inclusion of NoCs’ broad design space increases even more the complexity of design flows. Additionally, today electronic industry demands drastic time to market reduction and improved device diversity. On the other side, reconfigurable devices have had an impressive evolution and now, they are complex heterogeneous platforms which include a broad variety of embedded cores. Furthermore, today it is possible to embed reconfigurable arrays in application-specific integrated circuits and thus create highly flexible systems. These tendencies provide support to the idea of reconfigurable on-chip communication, which can reduce the system design time and permit to adapt their characteristics to currently running applications. This paper overviews some reconfigurable NoCs’ state of the art solutions and describes a reconfigurable on-chip communication approach, called DRNoC, which explores the highest possible flexibility and is not limited to NoCs. An important aspect considered in this paper is real implementations and therefore, all the solutions discussed along it, including DRNoC, have been validated on FPGAs. The paper also highlights some technology restrictions of currently available FPGA reconfiguration techniques that do not permit to test real-live examples on such systems.