A scalable VLSI speed/area tunable sorting network

This work presents a novel sorting network based on the “sorting by counting” algorithm. The proposed implementation of the algorithm is very regular. Further, its realization depends on a design parameter, that permits different tradeoffs between speed and area to be chosen. For example, we can fix this parameter to obtain a feasible SN with n inputs and O(log(n)) elaboration time with a reasonable multiplicative constant. Comparisons with previous works show that under some metrics for a wide range of values of n we obtain the best results.