Software-based self-testing of microprocessors

Hardware-based self-testing techniques have limitations in the performance and area overhead. Those can be eliminated using software-based self-testing. In this paper, we investigate capabilities of the microprocessor testing by software procedures taking into account system environment constraints. Special attention is paid to microarchitectural features of pipelined and superscalar processors. New test strategies are proposed combining deterministic and pseudorandom approaches supported by the available hardware mechanisms (test registers, on-chip monitoring circuitry, etc.), which improve testability features. The test effectiveness is studied using various test coverage measures (stimuli, circuit stressing), statistical and fault injection tools. To demonstrate the utility of the proposed methodology, it has been applied to commercial microprocessors and experimental results are presented in this paper.