DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design

As technology scales down to nanometer technology, coupling effects between neighboring wires become very important, and have a significant impact on the power consumption of on-chip interconnects. Especially, on-chip inductive effects need to be taken into account due to low-resistance metal interconnections and faster clock rates in today’s SoC design. In this paper, we propose a low power dynamic bus encoding scheme which simultaneously reduces capacitive and inductive effects by the measurement of the real RLC model. Our experimental results show that our approach can save the power consumption of the bus up to 12%.