Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology

• Wire scrambling cells are proposed as efficient element for encrypting the routing topology of netlist.
• A new netlist encryption design flow is proposed to prevent GDSII files against IP cloning and reverse engineering.
• An intelligent net selection criteria and heuristic algorithm is provided to improve hardware immunity with the minimum cost of overhead.

Reverse engineering is a great peril for hardware security especially when functional behavior extraction is required. In this paper a new automated mechanism is proposed to encrypt routing topology of the design which leads to hinder reverse engineering during the foundry/fabrication process. Moreover, new special standard cells (Wire Scrambling cells) are proposed corresponding with an automatic design flow to insert the WS-cells inside the netlist with the aim of maximum effectiveness of obfuscation and minimum overhead. The highlight feature of this mechanism is that it can be performed without detailed information about the functionality and structure of the design and hence, it can be automated easily. This methodology is implemented using an academic physical design framework (EduCAD). Experimental results show that reverse engineering can be hindered considerably in cost of negligible overheads in area, power consumption and total wire length.